Mr. Sateesh Kourav
APID: 2200
capResearch or Laboratory Scientist at Indian Institute of Information Technology, Design & Manufacturing, Jabalpur JABALPUR, MADHYA PRADESH
 

Expertise


Electronics

Area of Interest


FPGA

Short Biography


As a Junior Research Fellow in the Department of More Electronics and Communication Engineering, I contributed to research projects focused on embedded systems and VLSI design. Master of Technology (M.Tech) in Embedded System & VLSI Design Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2022] Specialized in Embedded Systems and VLSI Design, with a focus on digital electronics, hardware-software integration, and advanced circuit design. Bachelor of Engineering (B.E.) Electronics and Communication Engineering] Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2019] Completed foundational studies in engineering, gaining a broad understanding of electronics, digital systems, and related technologies. Publications: I have published 14 research articles in prestigious national and international journals, demonstrating my expertise and contributions to the field of Embedded Systems and VLSI Design. Hardware-Software Integration: Skilled in integrating hardware and software components to create efficient and reliable embedded systems. Programming Languages: Proficient in Verilog and VHDL for hardware description and system design. Design Tools: Experienced with a variety of design tools, including Diptrace, Origin, Layout Editor, Draw.io, Microsoft Visio, Symicade, and Cadence.

Honors and Awards


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Career Timeline


Assistant Professor at Gyan Ganga Institute of Technology & Sciences from 06/03/2023 to Present
Tilwara Ghat, Jabalpur, Madhya Pradesh 482003

Projects


Project: An ASIC design of Area and Speed Efficient Floating-Point Arithmetic and Logical Unit Implementation on Hybrid FPGAs
Goal: Area and Speed Efficient ALU
Current Stage: completed
Starting Date: 13/05/2020
Sponsored by: GGITS
Projects

Conference Details


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