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Mr.Sateesh Kourav
APID: 2200
capJUNIOR RESEARCH FELLOWSHIP (JRF) at Indian Institute of Information Technology, Design & Manufacturing, Jabalpur JABALPUR, MADHYA PRADESH
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My Biography

As a Junior Research Fellow in the Department of More Electronics and Communication Engineering, I contributed to research projects focused on embedded systems and VLSI design. Master of Technology (M.Tech) in Embedded System & VLSI Design Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2022] Specialized in Embedded Systems and VLSI Design, with a focus on digital electronics, hardware-software integration, and advanced circuit design. Bachelor of Engineering (B.E.) Electronics and Communication Engineering] Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2019] Completed foundational studies in engineering, gaining a broad understanding of electronics, digital systems, and related technologies. Publications: I have published 14 research articles in prestigious national and international journals, demonstrating my expertise and contributions to the field of Embedded Systems and VLSI Design. Hardware-Software Integration: Skilled in integrating hardware and software components to create efficient and reliable embedded systems. Programming Languages: Proficient in Verilog and VHDL for hardware description and system design. Design Tools: Experienced with a variety of design tools, including Diptrace, Origin, Layout Editor, Draw.io, Microsoft Visio, Symicade, and Cadence.

Area Of Expertise

Electronics

Area of Intrest

FPGA

Honors and Awards

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Career Timeline

Academic Identity

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Project: An ASIC design of Area and Speed Efficient Floating-Point Arithmetic and Logical Unit Implementation on Hybrid FPGAs
Goal: Area and Speed Efficient ALU
Current Stage: completed
Starting Date: 13/05/2020
Sponsored by: GGITS
Projects
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Mrudula Kulkarni


I am working as Dean of University and Professor of Civil Engineering at present.

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Mrudula Kulkarni


Hallo everyone Dr. Mrudula Kulkarni here, recently i have been working on technology development Read More project of LGS and ferrocement ( precast) Load bearing structural units and construction technique. We recently got approval for this technology by Building materials and technology Promotion Council.
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Pratik Dhokne


Hiiii everyone

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Vadlamani Nagalakshmi


Hello everyone

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KALYANI ALISETTY


Hello Sir,

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Mohd Basir Ahmed Siddiqui


Dr.Siddiqui MBA working as Professor of Livestock Production Management from last 21 yrs at Read More Veterinary College, Parbhani.Involved in teaching,research and extension.
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Sheetal Tank


My recent work is in How libraries can support in research related to Sustainable development Goals. Read More This will be helpful in increasing the usage of library resources and aboost the multidiciplinary and transdisciplinary research at the University
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Kapilesh Mangal


Hi, Dr. Kapilesh Mangal this side working with MGM University Institute of Hotel Management, Read More Aurangabad and has an experience of over 15 years in teaching. I have strong passion to work in the research area of management and especially in Hotel Management.
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Venkateshwar Amingad


Dr. A.Venkateshwar working as Associate Professor in the department of Computer Science and Read More Engineering of Ballari Institute of Technology and Management, Ballari Karnataka, India, has an experience of 19 years in the technical education and has been undergoing research since 2018 in the field of wireless sensor networks and Internet of Things for the agriculture domain. Main aim of the research carried out is to help and assist resource poor farmers of Karnataka who always experience water deficiency for crop irrigation. Implementing an Automation of Irrigation system through advance technologies like IoT, Artificial Intelligence and Machine learning becomes the prime goal of research which shall benefit the farmers and agro Industries to excel.
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Indubhushan Kumar


Thanks for my role.

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Publications
Project: An ASIC design of Area and Speed Efficient Floating-Point Arithmetic and Logical Unit Implementation on Hybrid FPGAs
Goal: Area and Speed Efficient ALU
Current Stage: completed
Starting Date: 13/05/2020
Sponsored by: GGITS
Projects
User has not updated his/her Conferences.
Editorial Roles
Electronics & Telecommunication Engineering

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