Pop-up Image
Mr.Sateesh Kourav
APID: 2200
capJUNIOR RESEARCH FELLOWSHIP (JRF) at Indian Institute of Information Technology, Design & Manufacturing, Jabalpur JABALPUR, MADHYA PRADESH
Please login
 
Home / APID Profiles

My Biography

As a Junior Research Fellow in the Department of More Electronics and Communication Engineering, I contributed to research projects focused on embedded systems and VLSI design. Master of Technology (M.Tech) in Embedded System & VLSI Design Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2022] Specialized in Embedded Systems and VLSI Design, with a focus on digital electronics, hardware-software integration, and advanced circuit design. Bachelor of Engineering (B.E.) Electronics and Communication Engineering] Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2019] Completed foundational studies in engineering, gaining a broad understanding of electronics, digital systems, and related technologies. Publications: I have published 14 research articles in prestigious national and international journals, demonstrating my expertise and contributions to the field of Embedded Systems and VLSI Design. Hardware-Software Integration: Skilled in integrating hardware and software components to create efficient and reliable embedded systems. Programming Languages: Proficient in Verilog and VHDL for hardware description and system design. Design Tools: Experienced with a variety of design tools, including Diptrace, Origin, Layout Editor, Draw.io, Microsoft Visio, Symicade, and Cadence.

Area Of Expertise

Electronics

Area of Intrest

FPGA

Honors and Awards

User has not updated his/her Awards & Honors.

Career Timeline

Academic Identity

User not updated academic id.
Project: An ASIC design of Area and Speed Efficient Floating-Point Arithmetic and Logical Unit Implementation on Hybrid FPGAs
Goal: Area and Speed Efficient ALU
Current Stage: completed
Starting Date: 13/05/2020
Sponsored by: GGITS
Projects
User has not updated his/her Conferences.

Feed


Dr Mohan S


Hello to all

Like: 0

#Apid #Academic #researchers #scholars #academicians #students


Dr Mohan S


My Peers always eager to discuss and promote their research with me.

Like: 0

#Apid #Academic #researchers #scholars #academicians #students


Sukanta Sarkar


I am a researcher with an interest in contributing to a deeper understanding of social issues. Human Read More behaviour is often characterized by deviations from perfect rationality and influenced by numerous factors that cloud the researcher’s view of underlying causalities. The majority of my current research applies field and lab-in-the-field experiments to test insights from classical and behavioural economics in the contexts of economic development and the design of innovation contests,
Like: 0

#Apid #Academic #researchers #scholars #academicians #students


Prof. R.V.S.S.N. Ravikumar


Hello to all

Like: 0

#Apid #Academic #researchers #scholars #academicians #students


Edgard Gonzales


Hello to the world

Like: 0

#Apid #Academic #researchers #scholars #academicians #students


Koudagani Mamatha


Hello all!!

Like: 0

#Apid #Academic #researchers #scholars #academicians #students


Bahar Kuloğlu


Numbers, Algebraic Number Theory, Group Theory, Matrix Theory, Graph ΤheoryPure MathematicsSet Read More Theory
Like: 0

#Apid #Academic #researchers #scholars #academicians #students


Mariana Levkiv


Hello to the world

Like: 0

#Apid #Academic #researchers #scholars #academicians #students


Tanushri Kamble


Hello All

Like: 0

#Apid #Academic #researchers #scholars #academicians #students


ANBUMANI ARUMUGAM


Happy Morning !!! Thank you very much for being a Reviewer in your STM journal “Journal of Image Read More Processing & Pattern Recognition Progress”.
Like: 0

#Apid #Academic #researchers #scholars #academicians #students

User has not Posted Anything.
Publications
Project: An ASIC design of Area and Speed Efficient Floating-Point Arithmetic and Logical Unit Implementation on Hybrid FPGAs
Goal: Area and Speed Efficient ALU
Current Stage: completed
Starting Date: 13/05/2020
Sponsored by: GGITS
Projects
User has not updated his/her Conferences.
Editorial Roles
Electronics & Telecommunication Engineering

No Reviewing details added by the User