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Mr.Sateesh Kourav
APID: 7617
capJUNIOR RESEARCH FELLOWSHIP (JRF) at Indian Institute of Information Technology, Design & Manufacturing, Jabalpur JABALPUR, MADHYA PRADESH
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My Biography

As a Junior Research Fellow in the Department of More Electronics and Communication Engineering, I contributed to research projects focused on embedded systems and VLSI design. Master of Technology (M.Tech) in Embedded System & VLSI Design Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2022] Specialized in Embedded Systems and VLSI Design, with a focus on digital electronics, hardware-software integration, and advanced circuit design. Bachelor of Engineering (B.E.) Electronics and Communication Engineering] Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2019] Completed foundational studies in engineering, gaining a broad understanding of electronics, digital systems, and related technologies. Publications: I have published 14 research articles in prestigious national and international journals, demonstrating my expertise and contributions to the field of Embedded Systems and VLSI Design.
Hardware-Software Integration: Skilled in integrating hardware and software components to create efficient and reliable embedded systems.
Programming Languages: Proficient in Verilog and VHDL for hardware description and system design.
Design Tools: Experienced with a variety of design tools, including Diptrace, Origin, Layout Editor, Draw.io, Microsoft Visio, Symicade, and Cadence.

Area Of Expertise

Electronics

Area of Intrest

FPGA

Honors and Awards

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Career Timeline

Academic Identity

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Project: An ASIC design of Area and Speed Efficient Floating-Point Arithmetic and Logical Unit Implementation on Hybrid FPGAs
Goal: Area and Speed Efficient ALU
Current Stage: completed
Starting Date: 13/05/2020
Sponsored by: GGITS
Projects
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Franca Nwankwo

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DEBYENDU CHAKROBORTY

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My present research work involved an instrumentation system with industrial IIoT with an Read More integrated Cloud System. Mainly focused on Environmental Pollution, Vibration of Machinery, Sensor modeling, etc. Presently active in research that eliminates the low-pressure area of sea/ocean storms or hurricanes and neutralizes their severity on sea/ocean bed. It is an AI & IoT-operated anti-circulatory (with respect to storm direction of rotation) high-speed floating motorized fan to restrict heavy flooding in the coastal parts of India.
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Amedeo Lonardo

Hello to all our Colleagues. A few days ago I got retired from Hospital job and now I am willing to Read More get more involved in the editorial word and publishing process.

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D.P.S. Rathore

After superannuation on 31 march, 2015, Actively involved in delivering invited talks in Inspire Read More programme of DST, Govt of India, Invited talks in National and International Conferences including IAEA conference, publication of articles and reviewing publications.
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Abdul Suhag

Through the innovative ideas

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Meu trabalho envolve o desenvolvimento de colunas cromatográfica para processos de purificação de Read More biomoléculas visando produtos eficientes e de baixo custo que venha facilitar o isolamento de diversas moléculas de interesse na aplicação em industrias alimentícias e farmacêuticas, promovendo desta forma, produtos mais baratos e de fácil acesso.
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Sara Kazemi Yazdi

Currently at University of Nottingham Malaysia (UNM), Dr. Sara K Yazdi is an Assistant Professor in Read More the Department of Chemical and Environmental Engineering. Besides, teaching and convening a variety of Engineering courses to PG and UG students, Sara’s research interest stretches across designing nature-based solutions (NBS) for circular water and wastewater management, biomass energy with carbon capture and monitoring for climate mitigation, biomimetic water purification systems and resource recovery from wastewater. She holds a PhD in Civil and Environmental Engineering.
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Karpagavalli Nageswaran

mental health Nurse, Nurse Educator and administrator able to contribute to body of knowledge in Read More Nursing
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Publications

Project: An ASIC design of Area and Speed Efficient Floating-Point Arithmetic and Logical Unit Implementation on Hybrid FPGAs
Goal: Area and Speed Efficient ALU
Current Stage: completed
Starting Date: 13/05/2020
Sponsored by: GGITS
Projects

User has not updated his/her Conferences.

Editorial Roles
Electronics & Telecommunication Engineering

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